✨ About The Role
- The role involves developing analog and clocking blocks for high-speed wireline and SerDes connectivity applications.
- The candidate will be responsible for designing low jitter, low power PLL, VCO, and clocking circuitry in advanced CMOS nodes.
- A deep understanding of advanced clock distribution techniques is required.
- Proficiency in electromagnetic tools like EMX is necessary for this position.
- The job includes design and tape out experience in advanced nodes such as 5nm and 3nm FinFET.
âš¡ Requirements
- The ideal candidate will have a Master's or PhD in Electrical Engineering or Computer Engineering.
- A minimum of 10 years of experience in high-speed analog mixed-signal design is essential.
- Experience with advanced node high-speed analog and mixed signal development for SerDes and data center networking is required.
- Strong analytical thinking and problem-solving skills are necessary for success in this role.
- The candidate should be organized, self-motivated, and able to work effectively across teams.