✨ About The Role
- The role involves designing low jitter, low power PLL, VCO, and clocking circuitry in advanced CMOS nodes.
- The engineer will need to have a deep understanding of advanced clock distribution techniques.
- Proficiency in electromagnetic tools like EMX or similar is required.
- The position includes assessing design bugs and recommending fixes or workarounds.
- The engineer will be involved in design management with knowledge of development methodologies and design flows.
âš¡ Requirements
- The ideal candidate will have a Master's or PhD in Electrical Engineering or Computer Engineering.
- A minimum of 7-10 years of experience in advanced node CMOS high-speed analog and mixed-signal development is essential.
- The candidate should possess recent design ownership in 5nm and 3nm technologies.
- Strong analytical thinking and problem-solving skills are crucial for success in this role.
- The candidate must be organized, self-motivated, and able to work effectively across internal and external teams.