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ASIC Digital Physical Design Engineer
Develop and implement advanced physical design methodologies for cutting-edge semiconductor technologies.
San Jose, California, United States
Expert
$141,000 - 225,000 USD / year
3 months ago
✨ About The Role
- The role involves developing and implementing power-grid and high-speed clock constraints and specifications.
- Candidates will be responsible for debugging LVS/DRC issues at both the chip and block level.
- The position requires familiarity with static timing analysis methodologies and relevant tools.
- Understanding of mixed signal environments is a must for this job.
- The job includes working with TSMC 7nm-2nm technology and understanding its limitations.
âš¡ Requirements
- The ideal candidate will have a Master's or PhD in Electrical Engineering or Computer Engineering.
- A minimum of 10 years of experience in physical design is required for this role.
- Candidates should possess deep knowledge of industry standards in physical design and related methodologies.
- Experience with tools such as Virtuoso, Caliber, and Redhawk is essential.
- Strong interpersonal skills and a proactive approach to collaboration and innovation are necessary for success in this position.
ASIC Digital Physical Design Engineer
San Jose, California, United States
$141,000 - 225,000 USD / year
Engineering
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