✨ About The Role
- The position involves implementing and verifying DFT methodologies specifically for HBM, DDR, and SerDes designs.
- The engineer will collaborate with design and architecture teams to identify and define critical testability requirements.
- Responsibilities include utilizing advanced simulation tools to thoroughly verify DFT implementations and documenting verification processes.
- The role requires generating, verifying, and debugging test vectors before tape release and validating them on ATE during the silicon bring-up phase.
- The engineer will also assist with silicon failure analysis, diagnostics, and yield improvement efforts.
âš¡ Requirements
- The ideal candidate will have a strong background in Design for Test (DFT) methodologies, particularly in HBM, DDR, and SerDes designs.
- A proven track record in DFT verification and experience with advanced simulation tools is essential for success in this role.
- Excellent analytical and problem-solving skills are necessary to analyze DFT-related data and provide insights for continuous design improvements.
- Strong communication and teamwork abilities are crucial, as the role involves collaboration with cross-functional teams.
- The candidate should be proactive in staying updated with the latest trends and technologies in DFT, HBM, and SerDes.