✨ About The Role
- The role involves layout design of high precision analog/mixed signal circuits while adhering to multiple constraints.
- The candidate will be responsible for debugging LVS/DRC/ERC errors using verification tools.
- Collaboration with design and layout engineers is crucial to optimize layout for area and performance.
- The position requires working with CAD, packaging, and foundry teams to resolve layout and verification issues.
- Experience with ADC, DAC, amplifiers, filters, and other mixed signal blocks is highly preferred.
âš¡ Requirements
- The ideal candidate will have a bachelor's degree and over 8 years of experience in layout design of high precision analog/mixed signal circuits.
- A strong background in deep submicron processes, particularly in 40nm, 16nm, and 7nm FinFet technologies is essential.
- Candidates should possess solid knowledge of precision and low noise analog layout techniques.
- Proficiency in using Cadence Virtuoso XL GXL layout/schematic and Mentor Calibre tools is required.
- A self-motivated team player who can work with minimal supervision will thrive in this role.