✨ About The Role
- The IP Integration Lead Engineer will be part of a cross-functional design team focused on developing die-to-die PHY IP for ASIC products.
- Responsibilities include developing the physical composition of the PHY and methodologies for integrating them into complex 2.5D and 3DIC ASICs.
- The role requires collaboration with various teams, including analog design, digital design, and physical composition, to optimize signal IO patterns and power delivery.
- The successful candidate will analyze power integrity in different use cases and workloads, ensuring high performance of the PHYs.
- Documentation for PHY integration will also be a key responsibility, requiring clear and precise communication of technical details.
âš¡ Requirements
- The ideal candidate will have a Bachelor's or Master's degree in Electrical and Electronic Engineering or a related field.
- A minimum of 6-8 years of relevant work experience is required, demonstrating a strong background in ASIC design.
- The successful individual will possess excellent communication skills, both verbal and written, to effectively collaborate with cross-functional teams.
- A detail-oriented and methodical approach to work is essential, along with the ability to manage multiple technical issues simultaneously.
- Experience with scripting languages such as Skill, TCL, Ruby, Bash, or Python will be beneficial for this role.